The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, multi-gate field effect transistors (FET) have been developed for their high drive currents, small footprints, and excellent control of short-channel effects. Examples of multi-gate FET include the double-gate FET, the triple-gate FET, the omega-gate FET, and the gate-all-around (or surround-gate) FET including both the horizontal gate-all-around (HGAA) FET and the vertical gate-all-around (VGAA) FET. The multi-gate FETs are expected to scale the semiconductor process technology beyond the limitations of the conventional bulk metal-oxide-semiconductor FET (MOSFET) technology. However, as the transistor device structure scales down and becomes three dimensional, the transistor contact resistance exhibits increased impact on the device performance. With conventional contact formation scheme, transistor contact resistance in highly scaled multi-gate FETs may limit the devices' intrinsic performance well over 50%.